Current Openings

Responsible for the Signal and Power integrity of new products and development vehicles. 

Defines test chip/test vehicle strategy to qualify new technology building blocks.

Partners with internal and external organizations to optimize design and analyze performance vs yield trade-off.

Drive technology design rules with ecosystem partners and support package design, SI/PI studies on new packaging concepts to drive advanced packaging technologies to support new Chipletz products. 

Package and board/system level power delivery network AC and DC simulation for low voltage/high-current supplies, DC/DC power conversion. 

Package and board/system level signal simulation of future DDR5, HBM memory bus including silicon I/O, package substrates, RDLs and interposers.  

System-level signal integrity simulations of future high-speed SERDES links such as USB-4, PCIe5, xGMI3, etc. including silicon I/O, package substrates, RDLs and interposers.  Electromagnetic modeling of package substrate 3D structure, bump/uBump interface.  Implementation of a HVM solution-space methodology.

The candidate should have a proven track record in Signal and Power integrity analysis including leading high speed transmission line designs and leading package designers for the development of both products and advanced development vehicles that are pushing the state of the art. 

The candidate should have excellent verbal and written communication skills to articulate ideas to technology partners, colleagues, and product architects.

Expect some domestic travel. 

State-of-The-Art Package stack up planning for signal, power, ground and embedded allocations. 

Power distribution network design concepts, optimizing stack up and power/ground plane assignments for minimal voltage noise. 

Power noise analysis in transient and frequency domain with Die, Package, PCB and Voltage Regulator for decoupling optimization and layout guideline definitions. 

System-level timing budgeting, length matching, design implementation and layout guidance.  

Crosstalk analysis and reduction techniques. 

Simultaneous Switching Noise with I/O power domain, Silicon I/O, Package substrate, RDL and interposer co-simulation for Eye diagram and Jitter analysis. 

High-speed channel simulation for low Bit-Error-Rate (BER) and Eye-Diagram analysis.

5+ years of experience with B.S. in Engineering or 3+ years of experience with advanced degree

Solid background on transmission line, electromagnetics and microwave theory with in-depth knowledge in Package and PCB high-speed layout techniques. 

Solid background on power distribution network, inductor, capacitor and voltage regulator. 

Detailed understanding of S-parameter, Z-parameter, and Fourier transform (FFT). 

Familiar with Cadence Allegro layout navigation and electrical constraints. 

Experience with SI/PI simulation tools such as Synopsys HSPICE, Cadence Spectre, ANSYS HFSS/3D-Layout/Q3D, ANSYS SiWave, KeySight ADS, and/or Seasim. 

Experience with MSO/DSO, BERT, TDR, VNA, Spectrum Analyzer and Probe Station 

C/C++/Perl/Python programming 

Chip power grid knowledge with Redhawk 

Worked directly with substrate suppliers to optimize materials and process 

Direct experience with high-speed interfaces 32Gbps or faster 

In-depth knowledge of I/O buffer IBIS Power-Aware modeling 

Familiar with equalization techniques such as FIR, CTLE, DFE, FFE and noise categories in the system and channel, and to optimize EQ settings. 

Familiar with high-speed digital logic RX and TX modeling, and Bit-Error-Rate (BER) theory.